Index: radeon.h =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v retrieving revision 1.2 diff -u -r1.2 radeon.h --- radeon.h 23 Apr 2004 19:26:46 -0000 1.2 +++ radeon.h 13 Jun 2004 19:19:01 -0000 @@ -531,6 +531,13 @@ FBLinearPtr videoLinear; int videoKey; + /* Render */ + Bool RenderAccel; + FBLinearPtr RenderTex; + void (*RenderCallback)(ScrnInfoPtr); + Time RenderTimeout; + int fbLocation; /* XXX */ + /* general */ Bool showCache; OptionInfoPtr Options; @@ -566,6 +573,7 @@ extern void RADEONSelectBuffer(ScrnInfoPtr pScrn, int buffer); extern Bool RADEONAccelInit(ScreenPtr pScreen); +extern void RADEONInit3DEngineForRender(ScrnInfoPtr pScrn); extern void RADEONEngineInit(ScrnInfoPtr pScrn); extern Bool RADEONCursorInit(ScreenPtr pScreen); extern Bool RADEONDGAInit(ScreenPtr pScreen); Index: radeon.man =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man,v retrieving revision 1.2 diff -u -r1.2 radeon.man --- radeon.man 23 Apr 2004 19:26:46 -0000 1.2 +++ radeon.man 11 Jun 2004 17:08:34 -0000 @@ -309,6 +309,43 @@ .B frequency parameter may be specified as a float value with standard suffixes like "k", "kHz", "M", "MHz". +.TP +.BI "Option \*qRenderAccel\*q \*q" boolean \*q +Enable XRender acceleration. Currently it does not work on 9700/9500 +and newer cards. Note when using a digital panel, subpixel RGB +decimation is enabled by default, the render acceleration is +effectively turned off by XAA. Option SubPixelOrder can be used to +disable subpixel decimation. Since render acceleration on radeon +cards is still in test stage, the default is +.B off. +.TP +.BI "Option \*qSubPixelOrder\*q \*q" "string" \*q +Force subpixel order to specified order. +Subpixel order is used for subpixel decimation on flat panels. +.br +NONE \-\- No subpixel (CRT like displays) +.br +RGB \-\- in horizontal RGB order (most flat panels) +.br +BGR \-\- in horizontal BGR order (some flat panels) + +.br +This option is intended to be used in following cases: +.br +1. The default subpixel order is incorrect for your panel. +.br +2. Enable subpixel decimation on analog panels. +.br +3. Adjust to one display type in dual-head clone mode setup. +.br +4. Get better performance with XRender acceleration on +digital panels (use NONE setting). +.br +The default is +.B NONE +for CRT, +.B RGB +for digital panels .SH SEE ALSO __xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__) Index: radeon_accel.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c,v retrieving revision 1.2 diff -u -r1.2 radeon_accel.c --- radeon_accel.c 23 Apr 2004 19:26:46 -0000 1.2 +++ radeon_accel.c 12 Jun 2004 07:15:50 -0000 @@ -386,6 +386,9 @@ #define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) #define FINISH_ACCEL() +#ifdef RENDER +#include "radeon_render.c" +#endif #include "radeon_accelfuncs.c" #undef ACCEL_MMIO @@ -404,6 +407,9 @@ #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val) #define FINISH_ACCEL() ADVANCE_RING() +#ifdef RENDER +#include "radeon_render.c" +#endif #include "radeon_accelfuncs.c" #undef ACCEL_CP Index: radeon_accelfuncs.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accelfuncs.c,v retrieving revision 1.2 diff -u -r1.2 radeon_accelfuncs.c --- radeon_accelfuncs.c 23 Apr 2004 19:26:46 -0000 1.2 +++ radeon_accelfuncs.c 13 Jun 2004 18:41:33 -0000 @@ -1346,6 +1346,49 @@ | HARDWARE_PATTERN_SCREEN_ORIGIN | BIT_ORDER_IN_BYTE_LSBFIRST); #endif + +#ifdef RENDER + if (info->RenderAccel && info->directRenderingEnabled && + ((pScrn->bitsPerPixel == 32) || (pScrn->bitsPerPixel == 16))) { + /* XXX: The non-CP vertex dispatch doesn't seem to work. */ + /* XXX: We are actually violating Render semantics with this, but it + * can't be helped with current XAA. With Render you can make the + * Picture have whatever wacky r/g/b/a masks you want, pretty much. + * We're forced to assume window pictures as destinations are of the + * common type of PICT_r5g6b5 for 16bpp and PICT_a8r8g8b8 for 32bpp, + * due to the lack of a dst format arg to the Setup functions. + * PICT_x8r8g8b8 is certainly almost as likely for 32bpp because + * it's what's returned by + * XRenderFindStandardFormat(dpy, PictStandardRGB24). + */ + + a->CPUToScreenAlphaTextureFlags = XAA_RENDER_POWER_OF_2_TILE_ONLY; + a->CPUToScreenAlphaTextureFormats = RADEONTextureFormats; + a->CPUToScreenTextureFlags = XAA_RENDER_POWER_OF_2_TILE_ONLY; + a->CPUToScreenTextureFormats = RADEONTextureFormats; + + if (info->ChipFamily >= CHIP_FAMILY_R300) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "XRender for R9700/9500 and newer cards is not supported\n"); + return; + } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || + (info->ChipFamily == CHIP_FAMILY_RV280) || + (info->ChipFamily == CHIP_FAMILY_RS300) || + (info->ChipFamily == CHIP_FAMILY_R200)) { + a->SetupForCPUToScreenAlphaTexture = FUNC_NAME(R200SetupForCPUToScreenAlphaTexture); + a->SubsequentCPUToScreenAlphaTexture = FUNC_NAME(R200SubsequentCPUToScreenTexture); + + a->SetupForCPUToScreenTexture = FUNC_NAME(R200SetupForCPUToScreenTexture); + a->SubsequentCPUToScreenTexture = FUNC_NAME(R200SubsequentCPUToScreenTexture); + } else { + a->SetupForCPUToScreenAlphaTexture = FUNC_NAME(R100SetupForCPUToScreenAlphaTexture); + a->SubsequentCPUToScreenAlphaTexture = FUNC_NAME(R100SubsequentCPUToScreenTexture); + + a->SetupForCPUToScreenTexture = FUNC_NAME(R100SetupForCPUToScreenTexture); + a->SubsequentCPUToScreenTexture = FUNC_NAME(R100SubsequentCPUToScreenTexture); + } + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "XRender Acceleration Enabled\n"); + } +#endif } #undef FUNC_NAME Index: radeon_dri.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c,v retrieving revision 1.2 diff -u -r1.2 radeon_dri.c --- radeon_dri.c 23 Apr 2004 19:26:46 -0000 1.2 +++ radeon_dri.c 11 Jun 2004 17:08:34 -0000 @@ -353,6 +353,9 @@ RADEONInfoPtr info = RADEONPTR(pScrn); if (info->accel) info->accel->NeedToSync = TRUE; +#ifdef RENDER + if (info->RenderAccel) RADEONInit3DEngineForRender(pScrn); +#endif } /* Called when the X server goes to sleep to allow the X server's Index: radeon_driver.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c,v retrieving revision 1.2 diff -u -r1.2 radeon_driver.c --- radeon_driver.c 23 Apr 2004 19:26:46 -0000 1.2 +++ radeon_driver.c 12 Jun 2004 18:27:43 -0000 @@ -139,7 +139,11 @@ OPTION_VIDEO_KEY, OPTION_DISP_PRIORITY, OPTION_PANEL_SIZE, - OPTION_MIN_DOTCLOCK + OPTION_MIN_DOTCLOCK, +#ifdef RENDER + OPTION_RENDER_ACCEL, + OPTION_SUBPIXEL_ORDER +#endif } RADEONOpts; const OptionInfoRec RADEONOptions[] = { @@ -175,6 +179,10 @@ { OPTION_DISP_PRIORITY, "DisplayPriority", OPTV_ANYSTR, {0}, FALSE }, { OPTION_PANEL_SIZE, "PanelSize", OPTV_ANYSTR, {0}, FALSE }, { OPTION_MIN_DOTCLOCK, "ForceMinDotClock", OPTV_FREQ, {0}, FALSE }, +#ifdef RENDER + { OPTION_RENDER_ACCEL, "RenderAccel", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_SUBPIXEL_ORDER, "SubPixelOrder", OPTV_ANYSTR, {0}, FALSE }, +#endif { -1, NULL, OPTV_NONE, {0}, FALSE } }; @@ -2343,6 +2351,12 @@ } #endif +#ifdef RENDER + info->RenderAccel = xf86ReturnOptValBool (info->Options, + OPTION_RENDER_ACCEL, TRUE); +#endif + + return TRUE; } @@ -4284,6 +4298,12 @@ if (info->VideoTimerCallback) (*info->VideoTimerCallback)(pScrn, currentTime.milliseconds); + +#ifdef RENDER + if(info->RenderCallback) + (*info->RenderCallback)(pScrn); +#endif + } /* Called at the start of each server generation. */ @@ -4293,6 +4313,10 @@ RADEONInfoPtr info = RADEONPTR(pScrn); BoxRec MemBox; int y2; +#ifdef RENDER + int subPixelOrder = SubPixelUnknown; + char* s; +#endif RADEONTRACE(("RADEONScreenInit %x %d\n", pScrn->memPhysBase, pScrn->fbOffset)); @@ -4435,10 +4459,14 @@ fbPictureInit (pScreen, 0, 0); #ifdef RENDER - if (PictureGetSubpixelOrder (pScreen) == SubPixelUnknown) - { - int subPixelOrder; + if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) { + if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB; + else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR; + else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone; + PictureSetSubpixelOrder (pScreen, subPixelOrder); + } + if (PictureGetSubpixelOrder (pScreen) == SubPixelUnknown) { switch (info->DisplayType) { case MT_NONE: subPixelOrder = SubPixelUnknown; break; case MT_LCD: subPixelOrder = SubPixelHorizontalRGB; break; @@ -5154,7 +5182,7 @@ restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, (restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16)); - usleep(5000); /* Let the clock to lock */ + usleep(50000); /* Let the clock to lock */ OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, RADEON_VCLK_SRC_SEL_PPLLCLK, @@ -7033,6 +7061,11 @@ } #endif + if(info->RenderTex) { + xf86FreeOffscreenLinear(info->RenderTex); + info->RenderTex = NULL; + } + if (pScrn->vtSema) { RADEONRestore(pScrn); } Index: radeon_reg.h =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v retrieving revision 1.2 diff -u -r1.2 radeon_reg.h --- radeon_reg.h 23 Apr 2004 19:26:46 -0000 1.2 +++ radeon_reg.h 13 Jun 2004 21:38:47 -0000 @@ -1718,6 +1718,18 @@ # define RADEON_ROUND_PREC_8TH_PIX (1 << 30) # define RADEON_ROUND_PREC_4TH_PIX (2 << 30) # define RADEON_ROUND_PREC_HALF_PIX (3 << 30) +#define R200_RE_CNTL 0x1c50 +# define R200_STIPPLE_ENABLE 0x1 +# define R200_SCISSOR_ENABLE 0x2 +# define R200_PATTERN_ENABLE 0x4 +# define R200_PERSPECTIVE_ENABLE 0x8 +# define R200_POINT_SMOOTH 0x20 +# define R200_VTX_STQ0_D3D 0x00010000 +# define R200_VTX_STQ1_D3D 0x00040000 +# define R200_VTX_STQ2_D3D 0x00100000 +# define R200_VTX_STQ3_D3D 0x00400000 +# define R200_VTX_STQ4_D3D 0x01000000 +# define R200_VTX_STQ5_D3D 0x04000000 #define RADEON_SE_CNTL_STATUS 0x2140 # define RADEON_VC_NO_SWAP (0 << 0) # define RADEON_VC_16BIT_SWAP (1 << 0) @@ -1937,7 +1949,528 @@ #define RADEON_SE_ZBIAS_FACTOR 0x1db0 #define RADEON_SE_ZBIAS_CONSTANT 0x1db4 - +#define RADEON_SE_VTX_FMT 0x2080 +# define RADEON_SE_VTX_FMT_XY 0x00000000 +# define RADEON_SE_VTX_FMT_W0 0x00000001 +# define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002 +# define RADEON_SE_VTX_FMT_FPALPHA 0x00000004 +# define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008 +# define RADEON_SE_VTX_FMT_FPSPEC 0x00000010 +# define RADEON_SE_VTX_FMT_FPFOG 0x00000020 +# define RADEON_SE_VTX_FMT_PKSPEC 0x00000040 +# define RADEON_SE_VTX_FMT_ST0 0x00000080 +# define RADEON_SE_VTX_FMT_ST1 0x00000100 +# define RADEON_SE_VTX_FMT_Q1 0x00000200 +# define RADEON_SE_VTX_FMT_ST2 0x00000400 +# define RADEON_SE_VTX_FMT_Q2 0x00000800 +# define RADEON_SE_VTX_FMT_ST3 0x00001000 +# define RADEON_SE_VTX_FMT_Q3 0x00002000 +# define RADEON_SE_VTX_FMT_Q0 0x00004000 +# define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000 +# define RADEON_SE_VTX_FMT_N0 0x00040000 +# define RADEON_SE_VTX_FMT_XY1 0x08000000 +# define RADEON_SE_VTX_FMT_Z1 0x10000000 +# define RADEON_SE_VTX_FMT_W1 0x20000000 +# define RADEON_SE_VTX_FMT_N1 0x40000000 +# define RADEON_SE_VTX_FMT_Z 0x80000000 + +#define RADEON_SE_VF_CNTL 0x2084 +# define RADEON_VF_PRIM_TYPE_POINT_LIST 1 +# define RADEON_VF_PRIM_TYPE_LINE_LIST 2 +# define RADEON_VF_PRIM_TYPE_LINE_STRIP 3 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7 +# define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8 +# define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9 +# define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10 +# define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11 +# define RADEON_VF_PRIM_TYPE_LINE_LOOP 12 +# define RADEON_VF_PRIM_TYPE_QUAD_LIST 13 +# define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14 +# define RADEON_VF_PRIM_TYPE_POLYGON 15 +# define RADEON_VF_PRIM_WALK_STATE (0<<4) +# define RADEON_VF_PRIM_WALK_INDEX (1<<4) +# define RADEON_VF_PRIM_WALK_LIST (2<<4) +# define RADEON_VF_PRIM_WALK_DATA (3<<4) +# define RADEON_VF_COLOR_ORDER_RGBA (1<<6) +# define RADEON_VF_RADEON_MODE (1<<7) +# define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9) +# define RADEON_VF_PROG_STREAM_ENA (1<<10) +# define RADEON_VF_INDEX_SIZE_SHIFT 11 +# define RADEON_VF_NUM_VERTICES_SHIFT 16 + +#define RADEON_SE_PORT_DATA0 0x2000 + +#define R200_SE_VAP_CNTL 0x2080 +# define R200_VAP_TCL_ENABLE 0x00000001 +# define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010 +# define R200_VAP_FORCE_W_TO_ONE 0x00010000 +# define R200_VAP_D3D_TEX_DEFAULT 0x00020000 +# define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18 +# define R200_VAP_VF_MAX_VTX_NUM (9 << 18) +# define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000 +#define R200_VF_MAX_VTX_INDX 0x210c +#define R200_VF_MIN_VTX_INDX 0x2110 +#define R200_SE_VTE_CNTL 0x20b0 +# define R200_VPORT_X_SCALE_ENA 0x00000001 +# define R200_VPORT_X_OFFSET_ENA 0x00000002 +# define R200_VPORT_Y_SCALE_ENA 0x00000004 +# define R200_VPORT_Y_OFFSET_ENA 0x00000008 +# define R200_VPORT_Z_SCALE_ENA 0x00000010 +# define R200_VPORT_Z_OFFSET_ENA 0x00000020 +# define R200_VTX_XY_FMT 0x00000100 +# define R200_VTX_Z_FMT 0x00000200 +# define R200_VTX_W0_FMT 0x00000400 +# define R200_VTX_W0_NORMALIZE 0x00000800 +# define R200_VTX_ST_DENORMALIZED 0x00001000 +#define R200_SE_VAP_CNTL_STATUS 0x2140 +# define R200_VC_NO_SWAP (0 << 0) +# define R200_VC_16BIT_SWAP (1 << 0) +# define R200_VC_32BIT_SWAP (2 << 0) +#define R200_PP_TXFILTER_0 0x2c00 +# define R200_MAG_FILTER_NEAREST (0 << 0) +# define R200_MAG_FILTER_LINEAR (1 << 0) +# define R200_MAG_FILTER_MASK (1 << 0) +# define R200_MIN_FILTER_NEAREST (0 << 1) +# define R200_MIN_FILTER_LINEAR (1 << 1) +# define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) +# define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) +# define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) +# define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) +# define R200_MIN_FILTER_ANISO_NEAREST (8 << 1) +# define R200_MIN_FILTER_ANISO_LINEAR (9 << 1) +# define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) +# define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) +# define R200_MIN_FILTER_MASK (15 << 1) +# define R200_MAX_ANISO_1_TO_1 (0 << 5) +# define R200_MAX_ANISO_2_TO_1 (1 << 5) +# define R200_MAX_ANISO_4_TO_1 (2 << 5) +# define R200_MAX_ANISO_8_TO_1 (3 << 5) +# define R200_MAX_ANISO_16_TO_1 (4 << 5) +# define R200_MAX_ANISO_MASK (7 << 5) +# define R200_MAX_MIP_LEVEL_MASK (0x0f << 16) +# define R200_MAX_MIP_LEVEL_SHIFT 16 +# define R200_YUV_TO_RGB (1 << 20) +# define R200_YUV_TEMPERATURE_COOL (0 << 21) +# define R200_YUV_TEMPERATURE_HOT (1 << 21) +# define R200_YUV_TEMPERATURE_MASK (1 << 21) +# define R200_WRAPEN_S (1 << 22) +# define R200_CLAMP_S_WRAP (0 << 23) +# define R200_CLAMP_S_MIRROR (1 << 23) +# define R200_CLAMP_S_CLAMP_LAST (2 << 23) +# define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) +# define R200_CLAMP_S_CLAMP_BORDER (4 << 23) +# define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) +# define R200_CLAMP_S_CLAMP_GL (6 << 23) +# define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) +# define R200_CLAMP_S_MASK (7 << 23) +# define R200_WRAPEN_T (1 << 26) +# define R200_CLAMP_T_WRAP (0 << 27) +# define R200_CLAMP_T_MIRROR (1 << 27) +# define R200_CLAMP_T_CLAMP_LAST (2 << 27) +# define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) +# define R200_CLAMP_T_CLAMP_BORDER (4 << 27) +# define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) +# define R200_CLAMP_T_CLAMP_GL (6 << 27) +# define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) +# define R200_CLAMP_T_MASK (7 << 27) +# define R200_KILL_LT_ZERO (1 << 30) +# define R200_BORDER_MODE_OGL (0 << 31) +# define R200_BORDER_MODE_D3D (1 << 31) +#define R200_PP_TXFORMAT_0 0x2c04 +# define R200_TXFORMAT_I8 (0 << 0) +# define R200_TXFORMAT_AI88 (1 << 0) +# define R200_TXFORMAT_RGB332 (2 << 0) +# define R200_TXFORMAT_ARGB1555 (3 << 0) +# define R200_TXFORMAT_RGB565 (4 << 0) +# define R200_TXFORMAT_ARGB4444 (5 << 0) +# define R200_TXFORMAT_ARGB8888 (6 << 0) +# define R200_TXFORMAT_RGBA8888 (7 << 0) +# define R200_TXFORMAT_Y8 (8 << 0) +# define R200_TXFORMAT_AVYU4444 (9 << 0) +# define R200_TXFORMAT_VYUY422 (10 << 0) +# define R200_TXFORMAT_YVYU422 (11 << 0) +# define R200_TXFORMAT_DXT1 (12 << 0) +# define R200_TXFORMAT_DXT23 (14 << 0) +# define R200_TXFORMAT_DXT45 (15 << 0) +# define R200_TXFORMAT_FORMAT_MASK (31 << 0) +# define R200_TXFORMAT_FORMAT_SHIFT 0 +# define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) +# define R200_TXFORMAT_NON_POWER2 (1 << 7) +# define R200_TXFORMAT_WIDTH_MASK (15 << 8) +# define R200_TXFORMAT_WIDTH_SHIFT 8 +# define R200_TXFORMAT_HEIGHT_MASK (15 << 12) +# define R200_TXFORMAT_HEIGHT_SHIFT 12 +# define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */ +# define R200_TXFORMAT_F5_WIDTH_SHIFT 16 +# define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20) +# define R200_TXFORMAT_F5_HEIGHT_SHIFT 20 +# define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) +# define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) +# define R200_TXFORMAT_ST_ROUTE_SHIFT 24 +# define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) +# define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) +# define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) +#define R200_PP_TXFORMAT_X_0 0x2c08 +#define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ +#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ +#define R200_PP_TXOFFSET_0 0x2d00 +# define R200_TXO_ENDIAN_NO_SWAP (0 << 0) +# define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) +# define R200_TXO_ENDIAN_WORD_SWAP (2 << 0) +# define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0) +# define R200_TXO_OFFSET_MASK 0xffffffe0 +# define R200_TXO_OFFSET_SHIFT 5 + +#define R200_PP_TFACTOR_0 0x2ee0 +#define R200_PP_TFACTOR_1 0x2ee4 +#define R200_PP_TFACTOR_2 0x2ee8 +#define R200_PP_TFACTOR_3 0x2eec +#define R200_PP_TFACTOR_4 0x2ef0 +#define R200_PP_TFACTOR_5 0x2ef4 + +#define R200_PP_TXCBLEND_0 0x2f00 +# define R200_TXC_ARG_A_ZERO (0) +# define R200_TXC_ARG_A_CURRENT_COLOR (2) +# define R200_TXC_ARG_A_CURRENT_ALPHA (3) +# define R200_TXC_ARG_A_DIFFUSE_COLOR (4) +# define R200_TXC_ARG_A_DIFFUSE_ALPHA (5) +# define R200_TXC_ARG_A_SPECULAR_COLOR (6) +# define R200_TXC_ARG_A_SPECULAR_ALPHA (7) +# define R200_TXC_ARG_A_TFACTOR_COLOR (8) +# define R200_TXC_ARG_A_TFACTOR_ALPHA (9) +# define R200_TXC_ARG_A_R0_COLOR (10) +# define R200_TXC_ARG_A_R0_ALPHA (11) +# define R200_TXC_ARG_A_R1_COLOR (12) +# define R200_TXC_ARG_A_R1_ALPHA (13) +# define R200_TXC_ARG_A_R2_COLOR (14) +# define R200_TXC_ARG_A_R2_ALPHA (15) +# define R200_TXC_ARG_A_R3_COLOR (16) +# define R200_TXC_ARG_A_R3_ALPHA (17) +# define R200_TXC_ARG_A_R4_COLOR (18) +# define R200_TXC_ARG_A_R4_ALPHA (19) +# define R200_TXC_ARG_A_R5_COLOR (20) +# define R200_TXC_ARG_A_R5_ALPHA (21) +# define R200_TXC_ARG_A_TFACTOR1_COLOR (26) +# define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) +# define R200_TXC_ARG_A_MASK (31 << 0) +# define R200_TXC_ARG_A_SHIFT 0 +# define R200_TXC_ARG_B_ZERO (0 << 5) +# define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5) +# define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5) +# define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5) +# define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5) +# define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5) +# define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5) +# define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5) +# define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5) +# define R200_TXC_ARG_B_R0_COLOR (10 << 5) +# define R200_TXC_ARG_B_R0_ALPHA (11 << 5) +# define R200_TXC_ARG_B_R1_COLOR (12 << 5) +# define R200_TXC_ARG_B_R1_ALPHA (13 << 5) +# define R200_TXC_ARG_B_R2_COLOR (14 << 5) +# define R200_TXC_ARG_B_R2_ALPHA (15 << 5) +# define R200_TXC_ARG_B_R3_COLOR (16 << 5) +# define R200_TXC_ARG_B_R3_ALPHA (17 << 5) +# define R200_TXC_ARG_B_R4_COLOR (18 << 5) +# define R200_TXC_ARG_B_R4_ALPHA (19 << 5) +# define R200_TXC_ARG_B_R5_COLOR (20 << 5) +# define R200_TXC_ARG_B_R5_ALPHA (21 << 5) +# define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5) +# define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5) +# define R200_TXC_ARG_B_MASK (31 << 5) +# define R200_TXC_ARG_B_SHIFT 5 +# define R200_TXC_ARG_C_ZERO (0 << 10) +# define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10) +# define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10) +# define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10) +# define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10) +# define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10) +# define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10) +# define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10) +# define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10) +# define R200_TXC_ARG_C_R0_COLOR (10 << 10) +# define R200_TXC_ARG_C_R0_ALPHA (11 << 10) +# define R200_TXC_ARG_C_R1_COLOR (12 << 10) +# define R200_TXC_ARG_C_R1_ALPHA (13 << 10) +# define R200_TXC_ARG_C_R2_COLOR (14 << 10) +# define R200_TXC_ARG_C_R2_ALPHA (15 << 10) +# define R200_TXC_ARG_C_R3_COLOR (16 << 10) +# define R200_TXC_ARG_C_R3_ALPHA (17 << 10) +# define R200_TXC_ARG_C_R4_COLOR (18 << 10) +# define R200_TXC_ARG_C_R4_ALPHA (19 << 10) +# define R200_TXC_ARG_C_R5_COLOR (20 << 10) +# define R200_TXC_ARG_C_R5_ALPHA (21 << 10) +# define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10) +# define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10) +# define R200_TXC_ARG_C_MASK (31 << 10) +# define R200_TXC_ARG_C_SHIFT 10 +# define R200_TXC_COMP_ARG_A (1 << 16) +# define R200_TXC_COMP_ARG_A_SHIFT (16) +# define R200_TXC_BIAS_ARG_A (1 << 17) +# define R200_TXC_SCALE_ARG_A (1 << 18) +# define R200_TXC_NEG_ARG_A (1 << 19) +# define R200_TXC_COMP_ARG_B (1 << 20) +# define R200_TXC_COMP_ARG_B_SHIFT (20) +# define R200_TXC_BIAS_ARG_B (1 << 21) +# define R200_TXC_SCALE_ARG_B (1 << 22) +# define R200_TXC_NEG_ARG_B (1 << 23) +# define R200_TXC_COMP_ARG_C (1 << 24) +# define R200_TXC_COMP_ARG_C_SHIFT (24) +# define R200_TXC_BIAS_ARG_C (1 << 25) +# define R200_TXC_SCALE_ARG_C (1 << 26) +# define R200_TXC_NEG_ARG_C (1 << 27) +# define R200_TXC_OP_MADD (0 << 28) +# define R200_TXC_OP_CND0 (2 << 28) +# define R200_TXC_OP_LERP (3 << 28) +# define R200_TXC_OP_DOT3 (4 << 28) +# define R200_TXC_OP_DOT4 (5 << 28) +# define R200_TXC_OP_CONDITIONAL (6 << 28) +# define R200_TXC_OP_DOT2_ADD (7 << 28) +# define R200_TXC_OP_MASK (7 << 28) +#define R200_PP_TXCBLEND2_0 0x2f04 +# define R200_TXC_TFACTOR_SEL_SHIFT 0 +# define R200_TXC_TFACTOR_SEL_MASK 0x7 +# define R200_TXC_TFACTOR1_SEL_SHIFT 4 +# define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4) +# define R200_TXC_SCALE_SHIFT 8 +# define R200_TXC_SCALE_MASK (7 << 8) +# define R200_TXC_SCALE_1X (0 << 8) +# define R200_TXC_SCALE_2X (1 << 8) +# define R200_TXC_SCALE_4X (2 << 8) +# define R200_TXC_SCALE_8X (3 << 8) +# define R200_TXC_SCALE_INV2 (5 << 8) +# define R200_TXC_SCALE_INV4 (6 << 8) +# define R200_TXC_SCALE_INV8 (7 << 8) +# define R200_TXC_CLAMP_SHIFT 12 +# define R200_TXC_CLAMP_MASK (3 << 12) +# define R200_TXC_CLAMP_WRAP (0 << 12) +# define R200_TXC_CLAMP_0_1 (1 << 12) +# define R200_TXC_CLAMP_8_8 (2 << 12) +# define R200_TXC_OUTPUT_REG_MASK (7 << 16) +# define R200_TXC_OUTPUT_REG_NONE (0 << 16) +# define R200_TXC_OUTPUT_REG_R0 (1 << 16) +# define R200_TXC_OUTPUT_REG_R1 (2 << 16) +# define R200_TXC_OUTPUT_REG_R2 (3 << 16) +# define R200_TXC_OUTPUT_REG_R3 (4 << 16) +# define R200_TXC_OUTPUT_REG_R4 (5 << 16) +# define R200_TXC_OUTPUT_REG_R5 (6 << 16) +# define R200_TXC_OUTPUT_MASK_MASK (7 << 20) +# define R200_TXC_OUTPUT_MASK_RGB (0 << 20) +# define R200_TXC_OUTPUT_MASK_RG (1 << 20) +# define R200_TXC_OUTPUT_MASK_RB (2 << 20) +# define R200_TXC_OUTPUT_MASK_R (3 << 20) +# define R200_TXC_OUTPUT_MASK_GB (4 << 20) +# define R200_TXC_OUTPUT_MASK_G (5 << 20) +# define R200_TXC_OUTPUT_MASK_B (6 << 20) +# define R200_TXC_OUTPUT_MASK_NONE (7 << 20) +# define R200_TXC_REPL_NORMAL 0 +# define R200_TXC_REPL_RED 1 +# define R200_TXC_REPL_GREEN 2 +# define R200_TXC_REPL_BLUE 3 +# define R200_TXC_REPL_ARG_A_SHIFT 26 +# define R200_TXC_REPL_ARG_A_MASK (3 << 26) +# define R200_TXC_REPL_ARG_B_SHIFT 28 +# define R200_TXC_REPL_ARG_B_MASK (3 << 28) +# define R200_TXC_REPL_ARG_C_SHIFT 30 +# define R200_TXC_REPL_ARG_C_MASK (3 << 30) +#define R200_PP_TXABLEND_0 0x2f08 +# define R200_TXA_ARG_A_ZERO (0) +# define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */ +# define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */ +# define R200_TXA_ARG_A_DIFFUSE_ALPHA (4) +# define R200_TXA_ARG_A_DIFFUSE_BLUE (5) +# define R200_TXA_ARG_A_SPECULAR_ALPHA (6) +# define R200_TXA_ARG_A_SPECULAR_BLUE (7) +# define R200_TXA_ARG_A_TFACTOR_ALPHA (8) +# define R200_TXA_ARG_A_TFACTOR_BLUE (9) +# define R200_TXA_ARG_A_R0_ALPHA (10) +# define R200_TXA_ARG_A_R0_BLUE (11) +# define R200_TXA_ARG_A_R1_ALPHA (12) +# define R200_TXA_ARG_A_R1_BLUE (13) +# define R200_TXA_ARG_A_R2_ALPHA (14) +# define R200_TXA_ARG_A_R2_BLUE (15) +# define R200_TXA_ARG_A_R3_ALPHA (16) +# define R200_TXA_ARG_A_R3_BLUE (17) +# define R200_TXA_ARG_A_R4_ALPHA (18) +# define R200_TXA_ARG_A_R4_BLUE (19) +# define R200_TXA_ARG_A_R5_ALPHA (20) +# define R200_TXA_ARG_A_R5_BLUE (21) +# define R200_TXA_ARG_A_TFACTOR1_ALPHA (26) +# define R200_TXA_ARG_A_TFACTOR1_BLUE (27) +# define R200_TXA_ARG_A_MASK (31 << 0) +# define R200_TXA_ARG_A_SHIFT 0 +# define R200_TXA_ARG_B_ZERO (0 << 5) +# define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */ +# define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */ +# define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5) +# define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5) +# define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5) +# define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5) +# define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5) +# define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5) +# define R200_TXA_ARG_B_R0_ALPHA (10 << 5) +# define R200_TXA_ARG_B_R0_BLUE (11 << 5) +# define R200_TXA_ARG_B_R1_ALPHA (12 << 5) +# define R200_TXA_ARG_B_R1_BLUE (13 << 5) +# define R200_TXA_ARG_B_R2_ALPHA (14 << 5) +# define R200_TXA_ARG_B_R2_BLUE (15 << 5) +# define R200_TXA_ARG_B_R3_ALPHA (16 << 5) +# define R200_TXA_ARG_B_R3_BLUE (17 << 5) +# define R200_TXA_ARG_B_R4_ALPHA (18 << 5) +# define R200_TXA_ARG_B_R4_BLUE (19 << 5) +# define R200_TXA_ARG_B_R5_ALPHA (20 << 5) +# define R200_TXA_ARG_B_R5_BLUE (21 << 5) +# define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5) +# define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5) +# define R200_TXA_ARG_B_MASK (31 << 5) +# define R200_TXA_ARG_B_SHIFT 5 +# define R200_TXA_ARG_C_ZERO (0 << 10) +# define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */ +# define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */ +# define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10) +# define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10) +# define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10) +# define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10) +# define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10) +# define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10) +# define R200_TXA_ARG_C_R0_ALPHA (10 << 10) +# define R200_TXA_ARG_C_R0_BLUE (11 << 10) +# define R200_TXA_ARG_C_R1_ALPHA (12 << 10) +# define R200_TXA_ARG_C_R1_BLUE (13 << 10) +# define R200_TXA_ARG_C_R2_ALPHA (14 << 10) +# define R200_TXA_ARG_C_R2_BLUE (15 << 10) +# define R200_TXA_ARG_C_R3_ALPHA (16 << 10) +# define R200_TXA_ARG_C_R3_BLUE (17 << 10) +# define R200_TXA_ARG_C_R4_ALPHA (18 << 10) +# define R200_TXA_ARG_C_R4_BLUE (19 << 10) +# define R200_TXA_ARG_C_R5_ALPHA (20 << 10) +# define R200_TXA_ARG_C_R5_BLUE (21 << 10) +# define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10) +# define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10) +# define R200_TXA_ARG_C_MASK (31 << 10) +# define R200_TXA_ARG_C_SHIFT 10 +# define R200_TXA_COMP_ARG_A (1 << 16) +# define R200_TXA_COMP_ARG_A_SHIFT (16) +# define R200_TXA_BIAS_ARG_A (1 << 17) +# define R200_TXA_SCALE_ARG_A (1 << 18) +# define R200_TXA_NEG_ARG_A (1 << 19) +# define R200_TXA_COMP_ARG_B (1 << 20) +# define R200_TXA_COMP_ARG_B_SHIFT (20) +# define R200_TXA_BIAS_ARG_B (1 << 21) +# define R200_TXA_SCALE_ARG_B (1 << 22) +# define R200_TXA_NEG_ARG_B (1 << 23) +# define R200_TXA_COMP_ARG_C (1 << 24) +# define R200_TXA_COMP_ARG_C_SHIFT (24) +# define R200_TXA_BIAS_ARG_C (1 << 25) +# define R200_TXA_SCALE_ARG_C (1 << 26) +# define R200_TXA_NEG_ARG_C (1 << 27) +# define R200_TXA_OP_MADD (0 << 28) +# define R200_TXA_OP_CND0 (2 << 28) +# define R200_TXA_OP_LERP (3 << 28) +# define R200_TXA_OP_CONDITIONAL (6 << 28) +# define R200_TXA_OP_MASK (7 << 28) +#define R200_PP_TXABLEND2_0 0x2f0c +# define R200_TXA_TFACTOR_SEL_SHIFT 0 +# define R200_TXA_TFACTOR_SEL_MASK 0x7 +# define R200_TXA_TFACTOR1_SEL_SHIFT 4 +# define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4) +# define R200_TXA_SCALE_SHIFT 8 +# define R200_TXA_SCALE_MASK (7 << 8) +# define R200_TXA_SCALE_1X (0 << 8) +# define R200_TXA_SCALE_2X (1 << 8) +# define R200_TXA_SCALE_4X (2 << 8) +# define R200_TXA_SCALE_8X (3 << 8) +# define R200_TXA_SCALE_INV2 (5 << 8) +# define R200_TXA_SCALE_INV4 (6 << 8) +# define R200_TXA_SCALE_INV8 (7 << 8) +# define R200_TXA_CLAMP_SHIFT 12 +# define R200_TXA_CLAMP_MASK (3 << 12) +# define R200_TXA_CLAMP_WRAP (0 << 12) +# define R200_TXA_CLAMP_0_1 (1 << 12) +# define R200_TXA_CLAMP_8_8 (2 << 12) +# define R200_TXA_OUTPUT_REG_MASK (7 << 16) +# define R200_TXA_OUTPUT_REG_NONE (0 << 16) +# define R200_TXA_OUTPUT_REG_R0 (1 << 16) +# define R200_TXA_OUTPUT_REG_R1 (2 << 16) +# define R200_TXA_OUTPUT_REG_R2 (3 << 16) +# define R200_TXA_OUTPUT_REG_R3 (4 << 16) +# define R200_TXA_OUTPUT_REG_R4 (5 << 16) +# define R200_TXA_OUTPUT_REG_R5 (6 << 16) +# define R200_TXA_DOT_ALPHA (1 << 20) +# define R200_TXA_REPL_NORMAL 0 +# define R200_TXA_REPL_RED 1 +# define R200_TXA_REPL_GREEN 2 +# define R200_TXA_REPL_ARG_A_SHIFT 26 +# define R200_TXA_REPL_ARG_A_MASK (3 << 26) +# define R200_TXA_REPL_ARG_B_SHIFT 28 +# define R200_TXA_REPL_ARG_B_MASK (3 << 28) +# define R200_TXA_REPL_ARG_C_SHIFT 30 +# define R200_TXA_REPL_ARG_C_MASK (3 << 30) + +#define R200_SE_VTX_FMT_0 0x2088 +# define R200_VTX_XY 0 /* always have xy */ +# define R200_VTX_Z0 (1<<0) +# define R200_VTX_W0 (1<<1) +# define R200_VTX_WEIGHT_COUNT_SHIFT (2) +# define R200_VTX_PV_MATRIX_SEL (1<<5) +# define R200_VTX_N0 (1<<6) +# define R200_VTX_POINT_SIZE (1<<7) +# define R200_VTX_DISCRETE_FOG (1<<8) +# define R200_VTX_SHININESS_0 (1<<9) +# define R200_VTX_SHININESS_1 (1<<10) +# define R200_VTX_COLOR_NOT_PRESENT 0 +# define R200_VTX_PK_RGBA 1 +# define R200_VTX_FP_RGB 2 +# define R200_VTX_FP_RGBA 3 +# define R200_VTX_COLOR_MASK 3 +# define R200_VTX_COLOR_0_SHIFT 11 +# define R200_VTX_COLOR_1_SHIFT 13 +# define R200_VTX_COLOR_2_SHIFT 15 +# define R200_VTX_COLOR_3_SHIFT 17 +# define R200_VTX_COLOR_4_SHIFT 19 +# define R200_VTX_COLOR_5_SHIFT 21 +# define R200_VTX_COLOR_6_SHIFT 23 +# define R200_VTX_COLOR_7_SHIFT 25 +# define R200_VTX_XY1 (1<<28) +# define R200_VTX_Z1 (1<<29) +# define R200_VTX_W1 (1<<30) +# define R200_VTX_N1 (1<<31) +#define R200_SE_VTX_FMT_1 0x208c +# define R200_VTX_TEX0_COMP_CNT_SHIFT 0 +# define R200_VTX_TEX1_COMP_CNT_SHIFT 3 +# define R200_VTX_TEX2_COMP_CNT_SHIFT 6 +# define R200_VTX_TEX3_COMP_CNT_SHIFT 9 +# define R200_VTX_TEX4_COMP_CNT_SHIFT 12 +# define R200_VTX_TEX5_COMP_CNT_SHIFT 15 + +#define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 +#define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 +#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 +# define R200_OUTPUT_XYZW (1<<0) +# define R200_OUTPUT_COLOR_0 (1<<8) +# define R200_OUTPUT_COLOR_1 (1<<9) +# define R200_OUTPUT_TEX_0 (1<<16) +# define R200_OUTPUT_TEX_1 (1<<17) +# define R200_OUTPUT_TEX_2 (1<<18) +# define R200_OUTPUT_TEX_3 (1<<19) +# define R200_OUTPUT_TEX_4 (1<<20) +# define R200_OUTPUT_TEX_5 (1<<21) +# define R200_OUTPUT_TEX_MASK (0x3f<<16) +# define R200_OUTPUT_DISCRETE_FOG (1<<24) +# define R200_OUTPUT_PT_SIZE (1<<25) +# define R200_FORCE_INORDER_PROC (1<<31) +#define R200_PP_CNTL_X 0x2cc4 +#define R200_PP_TXMULTI_CTL_0 0x2c1c +#define R200_SE_VTX_STATE_CNTL 0x2180 +# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) /* Registers for CP and Microcode Engine */ #define RADEON_CP_ME_RAM_ADDR 0x07d4 @@ -2013,6 +2546,7 @@ #define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 #define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 #define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 +#define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500 #define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 #define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 #define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 Index: radeon_render.c =================================================================== RCS file: radeon_render.c diff -N radeon_render.c --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ radeon_render.c 13 Jun 2004 22:01:22 -0000 @@ -0,0 +1,890 @@ + +#include "dixstruct.h" + +#include "xaa.h" +#include "xaalocal.h" + +#ifndef RENDER_GENERIC_HELPER +#define RENDER_GENERIC_HELPER + +static void RadeonInit3DEngineMMIO(ScrnInfoPtr pScrn); +#ifdef XF86DRI +static void RadeonInit3DEngineCP(ScrnInfoPtr pScrn); +#endif + +struct blendinfo { + Bool dst_alpha; + Bool src_alpha; + CARD32 blend_cntl; +}; + +/* The first part of blend_cntl corresponds to Fa from the render "protocol" + * document, and the second part to Fb. + */ +static const struct blendinfo RadeonBlendOp[] = { + /* Clear */ + {0, 0, RADEON_SRC_BLEND_GL_ZERO | + RADEON_DST_BLEND_GL_ZERO}, + /* Src */ + {0, 0, RADEON_SRC_BLEND_GL_ONE | + RADEON_DST_BLEND_GL_ZERO}, + /* Dst */ + {0, 0, RADEON_SRC_BLEND_GL_ZERO | + RADEON_DST_BLEND_GL_ONE}, + /* Over */ + {0, 1, RADEON_SRC_BLEND_GL_ONE | + RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, + /* OverReverse */ + {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | + RADEON_DST_BLEND_GL_ONE}, + /* In */ + {1, 0, RADEON_SRC_BLEND_GL_DST_ALPHA | + RADEON_DST_BLEND_GL_ZERO}, + /* InReverse */ + {0, 1, RADEON_SRC_BLEND_GL_ZERO | + RADEON_DST_BLEND_GL_SRC_ALPHA}, + /* Out */ + {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | + RADEON_DST_BLEND_GL_ZERO}, + /* OutReverse */ + {0, 1, RADEON_SRC_BLEND_GL_ZERO | + RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, + /* Atop */ + {1, 1, RADEON_SRC_BLEND_GL_DST_ALPHA | + RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, + /* AtopReverse */ + {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | + RADEON_DST_BLEND_GL_SRC_ALPHA}, + /* Xor */ + {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | + RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, + /* Add */ + {0, 0, RADEON_SRC_BLEND_GL_ONE | + RADEON_DST_BLEND_GL_ONE}, +}; + +/* We only support the original ops through Add on the Radeon, but some + * Dis/Conjointops above Add can be supported using original ones, so map them. + * While Disjoint/Conjoint Clr/Src/Dst may be rather uncommon, we may be able to + * support Saturate and DisjointOverReverse, so leave this table. + */ +static const CARD8 RadeonOpMap[] = { + PictOpClear, /* 0x0: PictOpClear (PictOpMinimum) */ + PictOpSrc, + PictOpDst, + PictOpOver, + PictOpOverReverse, + PictOpIn, + PictOpInReverse, + PictOpOut, + PictOpOutReverse, + PictOpAtop, + PictOpAtopReverse, + PictOpXor, + PictOpAdd, /* 0xc: Add */ + -1, /* 0xd: Saturate (PictOpMaximum)*/ + -1, + -1, + PictOpClear, /* 0x10: PictOpDisjointClear (PictOpDisjointMinimum) */ + PictOpSrc, + PictOpDst, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, /* 0x1b: PictOpDisjointClear (PictOpDisjointMaximum) */ + -1, + -1, + -1, + -1, + PictOpClear, /* 0x20: PictOpDisjointClear (PictOpConjointMinimum) */ + PictOpSrc, + PictOpDst, /* 0x22: PictOpConjointDst */ +}; + +/* Note on texture formats: + * TXFORMAT_Y8 expands to (Y,Y,Y,1). TXFORMAT_I8 expands to (I,I,I,I) + * The RADEON and R200 TXFORMATS we use are the same on r100/r200. + */ + +static CARD32 RADEONTextureFormats[] = { + PICT_a8r8g8b8, + PICT_a8, + PICT_x8r8g8b8, + PICT_r5g6b5, + PICT_x1r5g5b5, +}; + +static void RadeonGetTextureFormat(CARD32 format, CARD32 *txformat, int *bytepp) +{ + switch (format) { + case PICT_a8r8g8b8: + *txformat = RADEON_TXFORMAT_ARGB8888 | RADEON_TXFORMAT_ALPHA_IN_MAP; + *bytepp = 4; + break; + case PICT_a8: + *txformat = RADEON_TXFORMAT_I8 | RADEON_TXFORMAT_ALPHA_IN_MAP; + *bytepp = 1; + break; + case PICT_x8r8g8b8: + *txformat = RADEON_TXFORMAT_ARGB8888; + *bytepp = 4; + break; + case PICT_r5g6b5: + *txformat = RADEON_TXFORMAT_RGB565; + *bytepp = 2; + break; + case PICT_a1r5g5b5: + *txformat = RADEON_TXFORMAT_ARGB1555 | RADEON_TXFORMAT_ALPHA_IN_MAP; + *bytepp = 2; + break; + case PICT_x1r5g5b5: + *txformat = RADEON_TXFORMAT_ARGB1555; + *bytepp = 2; + break; + } +} + +static long F_TO_DW(float val) +{ + union { + float f; + long l; + } tmp; + tmp.f = val; + return tmp.l; +} + +/* Compute log base 2 of val. */ +static int +ATILog2(int val) +{ + int bits; + + for (bits = 0; val != 0; val >>= 1, ++bits) + ; + return bits - 1; +} + +void RADEONInit3DEngineForRender(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR (pScrn); + +#ifdef XF86DRI + if (info->directRenderingEnabled) + RadeonInit3DEngineCP(pScrn); + else +#endif + RadeonInit3DEngineMMIO(pScrn); +} + +static void +RemoveLinear (FBLinearPtr linear) +{ + RADEONInfoPtr info = (RADEONInfoPtr)(linear->devPrivate.ptr); + + info->RenderTex = NULL; +} + +static void +RenderCallback (ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + + if ((currentTime.milliseconds > info->RenderTimeout) && info->RenderTex) { + xf86FreeOffscreenLinear(info->RenderTex); + info->RenderTex = NULL; + } + + if (!info->RenderTex) + info->RenderCallback = NULL; +} + +static Bool +AllocateLinear ( + ScrnInfoPtr pScrn, + int sizeNeeded +){ + RADEONInfoPtr info = RADEONPTR(pScrn); + + info->RenderTimeout = currentTime.milliseconds + 30000; + info->RenderCallback = RenderCallback; + + if (info->RenderTex) { + if (info->RenderTex->size >= sizeNeeded) + return TRUE; + else { + if (xf86ResizeOffscreenLinear(info->RenderTex, sizeNeeded)) + return TRUE; + + xf86FreeOffscreenLinear(info->RenderTex); + info->RenderTex = NULL; + } + } + + info->RenderTex = xf86AllocateOffscreenLinear(pScrn->pScreen, sizeNeeded, 32, + NULL, RemoveLinear, info); + + return (info->RenderTex != NULL); +} + +static int texwidth, texheight; +#endif + +#if defined(ACCEL_MMIO) && defined(ACCEL_CP) +#error Cannot define both MMIO and CP acceleration! +#endif + +#if !defined(UNIXCPP) || defined(ANSICPP) +#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix +#else +#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix +#endif + +#ifdef ACCEL_MMIO +#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO) +#else +#ifdef ACCEL_CP +#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP) +#else +#error No accel type defined! +#endif +#endif + + +static void FUNC_NAME(RadeonInit3DEngine)(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + ACCEL_PREAMBLE(); + + if (info->ChipFamily >= CHIP_FAMILY_R300) { + /* Unimplemented */ + } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || + (info->ChipFamily == CHIP_FAMILY_RV280) || + (info->ChipFamily == CHIP_FAMILY_RS300) || + (info->ChipFamily == CHIP_FAMILY_R200)) { + BEGIN_ACCEL(10); + OUT_ACCEL_REG(R200_VF_MAX_VTX_INDX, 0xffffff); /* XXX Necessary? */ + OUT_ACCEL_REG(R200_VF_MIN_VTX_INDX, 0x0); /* XXX Necessary? */ + OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0/*(1<<8)*/); /* Disable TCL? XXX: magic number */ + OUT_ACCEL_REG(R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 0x0); /* XXX Necessary? */ + OUT_ACCEL_REG(R200_PP_CNTL_X, 0); /* XXX Necessary? */ + OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0); /* XXX Necessary? */ + OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0); /* XXX Necessary? */ + OUT_ACCEL_REG(R200_RE_CNTL, 0x0); + OUT_ACCEL_REG(R200_SE_VTE_CNTL, R200_VTX_ST_DENORMALIZED); /* ??? */ + OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_VF_MAX_VTX_NUM); + FINISH_ACCEL(); + } else { + BEGIN_ACCEL(2); + OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); + OUT_ACCEL_REG(RADEON_SE_COORD_FMT, + RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | + RADEON_VTX_ST0_NONPARAMETRIC | + RADEON_VTX_ST1_NONPARAMETRIC | + RADEON_TEX1_W_ROUTING_USE_W0); + FINISH_ACCEL(); + } + + BEGIN_ACCEL(3); + OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); + OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); + OUT_ACCEL_REG(RADEON_SE_CNTL, RADEON_DIFFUSE_SHADE_GOURAUD | + RADEON_BFACE_SOLID | + RADEON_FFACE_SOLID | + RADEON_VTX_PIX_CENTER_OGL | + RADEON_ROUND_MODE_ROUND | + RADEON_ROUND_PREC_4TH_PIX); + FINISH_ACCEL(); +} + +static Bool FUNC_NAME(R100SetupTexture)(ScrnInfoPtr pScrn, + int format, + CARD8 *src, + int src_pitch, + int width, + int height, + int flags) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + CARD8 *dst; + CARD32 tex_size = 0, txformat; + int dst_pitch, offset, size, i, tex_bytepp; + ACCEL_PREAMBLE(); + + if ((width > 2048) || (height > 2048)) + return FALSE; + + RadeonGetTextureFormat(format, &txformat, &tex_bytepp); + + dst_pitch = ((width + 7) & ~7) * tex_bytepp; + size = dst_pitch * height; + + if (!AllocateLinear(pScrn, size)) + return FALSE; + + if (flags & XAA_RENDER_REPEAT) { + txformat |= ATILog2(width) << RADEON_TXFORMAT_WIDTH_SHIFT; + txformat |= ATILog2(height) << RADEON_TXFORMAT_HEIGHT_SHIFT; + } else { + tex_size = ((height - 1) << 16) | (width - 1); + txformat |= RADEON_TXFORMAT_NON_POWER2; + } + + offset = info->RenderTex->offset * pScrn->bitsPerPixel / 8; + + /* Upload texture to card */ + i = height; + dst = (CARD8*)(info->FB + offset); + if (info->accel->NeedToSync) + info->accel->Sync(pScrn); + while(i--) { + memcpy(dst, src, width * tex_bytepp); + src += src_pitch; + dst += dst_pitch; + } + + /*texwidth = width; + texheight = height;*/ + BEGIN_ACCEL(5); + OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, txformat); + OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0, tex_size); + OUT_ACCEL_REG(RADEON_PP_TEX_PITCH_0, dst_pitch - 32); + OUT_ACCEL_REG(RADEON_PP_TXOFFSET_0, offset + info->fbLocation + + pScrn->fbOffset); + OUT_ACCEL_REG(RADEON_PP_TXFILTER_0, RADEON_MAG_FILTER_LINEAR | + RADEON_MIN_FILTER_LINEAR | + RADEON_CLAMP_S_WRAP | + RADEON_CLAMP_T_WRAP); + FINISH_ACCEL(); + + return TRUE; +} + +static Bool +FUNC_NAME(R100SetupForCPUToScreenAlphaTexture) ( + ScrnInfoPtr pScrn, + int op, + CARD16 red, + CARD16 green, + CARD16 blue, + CARD16 alpha, + int alphaFormat, + CARD8 *alphaPtr, + int alphaPitch, + int width, + int height, + int flags +) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + CARD32 format, srccolor; + ACCEL_PREAMBLE(); + + if (op >= sizeof(RadeonOpMap) / sizeof(RadeonOpMap[0]) || + RadeonOpMap[op] == ((CARD8)-1)) + { + return FALSE; + } + + if (!FUNC_NAME(R100SetupTexture)(pScrn, alphaFormat, alphaPtr, alphaPitch, + width, height, flags)) + return FALSE; + + if (pScrn->bitsPerPixel == 32) + format = RADEON_COLOR_FORMAT_ARGB8888; + else + format = RADEON_COLOR_FORMAT_RGB565; + + srccolor = ((alpha & 0xff00) << 16) | ((red & 0xff00) << 8) | (blue >> 8) | + (green & 0xff00); + + BEGIN_ACCEL(8); + OUT_ACCEL_REG(RADEON_RB3D_CNTL, format | RADEON_ALPHA_BLEND_ENABLE); + OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth); + OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | + RADEON_TEX_BLEND_0_ENABLE); + OUT_ACCEL_REG(RADEON_PP_TFACTOR_0, srccolor); + OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_A_TFACTOR_COLOR | + RADEON_COLOR_ARG_B_T0_ALPHA); + OUT_ACCEL_REG(RADEON_PP_TXABLEND_0, RADEON_ALPHA_ARG_A_TFACTOR_ALPHA | + RADEON_ALPHA_ARG_B_T0_ALPHA); + OUT_ACCEL_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY | + RADEON_SE_VTX_FMT_ST0); + OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, + RadeonBlendOp[RadeonOpMap[op]].blend_cntl); + FINISH_ACCEL(); + + return TRUE; +} + + +static Bool +FUNC_NAME(R100SetupForCPUToScreenTexture) ( + ScrnInfoPtr pScrn, + int op, + int texFormat, + CARD8 *texPtr, + int texPitch, + int width, + int height, + int flags +) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + CARD32 format; + ACCEL_PREAMBLE(); + + if (op >= sizeof(RadeonOpMap) / sizeof(RadeonOpMap[0]) || + RadeonOpMap[op] == ((CARD8)-1)) + { + return FALSE; + } + + if (!FUNC_NAME(R100SetupTexture)(pScrn, texFormat, texPtr, texPitch, width, + height, flags)) + return FALSE; + + if (pScrn->bitsPerPixel == 32) + format = RADEON_COLOR_FORMAT_ARGB8888; + else + format = RADEON_COLOR_FORMAT_RGB565; + + BEGIN_ACCEL(7); + OUT_ACCEL_REG(RADEON_RB3D_CNTL, format | RADEON_ALPHA_BLEND_ENABLE); + OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth); + OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | + RADEON_TEX_BLEND_0_ENABLE); + if (texFormat != PICT_a8) + OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_C_T0_COLOR); + else + OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_C_ZERO); + OUT_ACCEL_REG(RADEON_PP_TXABLEND_0, RADEON_ALPHA_ARG_C_T0_ALPHA); + OUT_ACCEL_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY | + RADEON_SE_VTX_FMT_ST0); + OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, + RadeonBlendOp[RadeonOpMap[op]].blend_cntl); + FINISH_ACCEL(); + + return TRUE; +} + + +static void +FUNC_NAME(R100SubsequentCPUToScreenTexture) ( + ScrnInfoPtr pScrn, + int dstx, + int dsty, + int srcx, + int srcy, + int width, + int height +) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + int byteshift; + CARD32 fboffset; + float l, t, r, b, fl, fr, ft, fb; + + ACCEL_PREAMBLE(); + + byteshift = (pScrn->bitsPerPixel >> 4); + fboffset = (info->fbLocation + pScrn->fbOffset + + ((pScrn->displayWidth * dsty + dstx) << byteshift)) & ~15; + l = ((dstx << byteshift) % 16) >> byteshift; + t = 0.0; + r = (float)width + l; + b = (float)height; + fl = (float)srcx/* / (float)texwidth*/; + fr = (float)(srcx + width)/* / (float)texwidth*/; + ft = (float)srcy/* / (float)texheight*/; + fb = (float)(srcy + height)/* / (float)texheight*/; + + xf86DrvMsg(0, X_INFO, "subsequent: %4f %4f %d %d %4f %4f %4f %4f\n", l, t, + width, height, fl, ft, fr, fb); + +#ifdef ACCEL_CP + BEGIN_RING(23); + + /* Note: we can't simply setup 3D surface at the same location as the front buffer, + some apps may draw offscreen pictures out of the limitation of radeon 3D surface. + * Well, not with current XAA, but the screen itself may extend beyond the 2048x2048 limit. + */ + OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset); + + OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD, 17)); + /* RADEON_SE_VTX_FMT */ + OUT_RING(RADEON_CP_VC_FRMT_XY | + RADEON_CP_VC_FRMT_ST0); + /* SE_VF_CNTL */ + OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | + RADEON_CP_VC_CNTL_PRIM_WALK_RING | + RADEON_CP_VC_CNTL_MAOS_ENABLE | + RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | + (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); + + OUT_RING(F_TO_DW(l)); + OUT_RING(F_TO_DW(t)); + OUT_RING(F_TO_DW(fl)); + OUT_RING(F_TO_DW(ft)); + + OUT_RING(F_TO_DW(r)); + OUT_RING(F_TO_DW(t)); + OUT_RING(F_TO_DW(fr)); + OUT_RING(F_TO_DW(ft)); + + OUT_RING(F_TO_DW(r)); + OUT_RING(F_TO_DW(b)); + OUT_RING(F_TO_DW(fr)); + OUT_RING(F_TO_DW(fb)); + + OUT_RING(F_TO_DW(l)); + OUT_RING(F_TO_DW(b)); + OUT_RING(F_TO_DW(fl)); + OUT_RING(F_TO_DW(fb)); + + /*OUT_ACCEL_REG(RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH);*/ + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); + + ADVANCE_RING(); +#else + BEGIN_ACCEL(19); + + /* Note: we can't simply setup 3D surface at the same location as the front buffer, + some apps may draw offscreen pictures out of the limitation of radeon 3D surface. + */ + OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset); + + /* When cp is enabled, the final drawing can be done by sending a type-3 packet. + But it doesn't seem to give much noticeable performance improvement, + may not worth of bloating up the code. + */ + OUT_ACCEL_REG(RADEON_SE_VF_CNTL, RADEON_VF_PRIM_TYPE_TRIANGLE_FAN | + RADEON_VF_PRIM_WALK_DATA | + RADEON_VF_RADEON_MODE | + (4 << RADEON_VF_NUM_VERTICES_SHIFT)); + + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(l)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(t)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fl)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(ft)); + + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(r)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(t)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fr)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(ft)); + + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(r)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(b)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fr)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fb)); + + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(l)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(b)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fl)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fb)); + + /*OUT_ACCEL_REG(RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH);*/ + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); + FINISH_ACCEL(); +#endif + +} + +static Bool FUNC_NAME(R200SetupTexture)(ScrnInfoPtr pScrn, + int format, + CARD8 *src, + int src_pitch, + int width, + int height, + int flags) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + CARD8 *dst; + CARD32 tex_size = 0, txformat; + int dst_pitch, offset, size, i, tex_bytepp; + ACCEL_PREAMBLE(); + + if ((width > 2048) || (height > 2048)) + return FALSE; + + RadeonGetTextureFormat(format, &txformat, &tex_bytepp); + + dst_pitch = ((width + 7) & ~7) * tex_bytepp; + size = dst_pitch * height; + + if (!AllocateLinear(pScrn, size)) + return FALSE; + + if (flags & XAA_RENDER_REPEAT) { + txformat |= ATILog2(width) << R200_TXFORMAT_WIDTH_SHIFT; + txformat |= ATILog2(height) << R200_TXFORMAT_HEIGHT_SHIFT; + } else { + tex_size = ((height - 1) << 16) | (width - 1); + txformat |= RADEON_TXFORMAT_NON_POWER2; + } + + offset = info->RenderTex->offset * pScrn->bitsPerPixel / 8; + + /* Upload texture to card */ + i = height; + dst = (CARD8*)(info->FB + offset); + if (info->accel->NeedToSync) + info->accel->Sync(pScrn); + while(i--) { + memcpy(dst, src, width * tex_bytepp); + src += src_pitch; + dst += dst_pitch; + } + + texwidth = width; + texheight = height; + BEGIN_ACCEL(6); + OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat); + OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0); + OUT_ACCEL_REG(R200_PP_TXSIZE_0, tex_size); + OUT_ACCEL_REG(R200_PP_TXPITCH_0, dst_pitch - 32); + OUT_ACCEL_REG(R200_PP_TXOFFSET_0, offset + info->fbLocation + + pScrn->fbOffset); + OUT_ACCEL_REG(R200_PP_TXFILTER_0, R200_MAG_FILTER_NEAREST | + R200_MIN_FILTER_NEAREST | + R200_CLAMP_S_WRAP | + R200_CLAMP_T_WRAP); + FINISH_ACCEL(); + + return TRUE; +} + +static Bool +FUNC_NAME(R200SetupForCPUToScreenAlphaTexture) ( + ScrnInfoPtr pScrn, + int op, + CARD16 red, + CARD16 green, + CARD16 blue, + CARD16 alpha, + int alphaFormat, + CARD8 *alphaPtr, + int alphaPitch, + int width, + int height, + int flags +) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + CARD32 format, srccolor; + ACCEL_PREAMBLE(); + + if (op >= sizeof(RadeonOpMap) / sizeof(RadeonOpMap[0]) || + RadeonOpMap[op] == ((CARD8)-1)) + { + return FALSE; + } + + if (!FUNC_NAME(R200SetupTexture)(pScrn, alphaFormat, alphaPtr, alphaPitch, + width, height, flags)) + return FALSE; + + if (pScrn->bitsPerPixel == 32) + format = RADEON_COLOR_FORMAT_ARGB8888; + else + format = RADEON_COLOR_FORMAT_RGB565; + + srccolor = ((alpha & 0xff00) << 16) | ((red & 0xff00) << 8) | (blue >> 8) | + (green & 0xff00); + + BEGIN_ACCEL(11); + OUT_ACCEL_REG(RADEON_RB3D_CNTL, format | RADEON_ALPHA_BLEND_ENABLE); + OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth); + OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | + RADEON_TEX_BLEND_0_ENABLE); + OUT_ACCEL_REG(R200_PP_TFACTOR_0, srccolor); + OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_A_TFACTOR_COLOR | + R200_TXC_ARG_B_R0_ALPHA); + OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, 0); + OUT_ACCEL_REG(R200_PP_TXABLEND_0, R200_TXA_ARG_A_TFACTOR_ALPHA | + R200_TXA_ARG_B_R0_ALPHA); + OUT_ACCEL_REG(R200_PP_TXABLEND2_0, 0); + OUT_ACCEL_REG(R200_SE_VTX_FMT_0, 0); + OUT_ACCEL_REG(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); + OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, + RadeonBlendOp[RadeonOpMap[op]].blend_cntl); + FINISH_ACCEL(); + + return TRUE; +} + +static Bool +FUNC_NAME(R200SetupForCPUToScreenTexture) ( + ScrnInfoPtr pScrn, + int op, + int texFormat, + CARD8 *texPtr, + int texPitch, + int width, + int height, + int flags +) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + CARD32 format; + ACCEL_PREAMBLE(); + + if (texFormat == PICT_a8) + return FALSE; /* XXX: Why doesn't this work? */ + if (op >= sizeof(RadeonOpMap) / sizeof(RadeonOpMap[0]) || + RadeonOpMap[op] == ((CARD8)-1)) + { + return FALSE; + } + + if (!FUNC_NAME(R200SetupTexture)(pScrn, texFormat, texPtr, texPitch, width, + height, flags)) + return FALSE; + + if (pScrn->bitsPerPixel == 32) + format = RADEON_COLOR_FORMAT_ARGB8888; + else + format = RADEON_COLOR_FORMAT_RGB565; + + BEGIN_ACCEL(10); + OUT_ACCEL_REG(RADEON_RB3D_CNTL, format | RADEON_ALPHA_BLEND_ENABLE); + OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth); + OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | + RADEON_TEX_BLEND_0_ENABLE); + if (texFormat != PICT_a8) + OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_C_R0_COLOR); + else + OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_C_ZERO); + OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, 0); + OUT_ACCEL_REG(R200_PP_TXABLEND_0, R200_TXA_ARG_C_R0_ALPHA); + OUT_ACCEL_REG(R200_PP_TXABLEND2_0, 0); + OUT_ACCEL_REG(R200_SE_VTX_FMT_0, 0); + OUT_ACCEL_REG(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); + OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, + RadeonBlendOp[RadeonOpMap[op]].blend_cntl); + FINISH_ACCEL(); + + return TRUE; +} + +static void +FUNC_NAME(R200SubsequentCPUToScreenTexture) ( + ScrnInfoPtr pScrn, + int dstx, + int dsty, + int srcx, + int srcy, + int width, + int height +) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + int byteshift; + CARD32 fboffset; + float l, t, r, b, fl, fr, ft, fb; + ACCEL_PREAMBLE(); + + byteshift = (pScrn->bitsPerPixel >> 4); + fboffset = (info->fbLocation + pScrn->fbOffset + ((pScrn->displayWidth * + dsty + dstx) << byteshift)) & ~15; + l = ((dstx << byteshift) % 16) >> byteshift; + t = 0.0; + r = (float)width + l; + b = (float)height; + fl = (float)srcx/* / (float)texwidth*/; + fr = (float)(srcx + width)/* / (float)texwidth*/; + ft = (float)srcy/* / (float)texheight*/; + fb = (float)(srcy + height)/* / (float)texheight*/; + + xf86DrvMsg(0, X_INFO, "subsequent: %4f %4f %d %d %4f %4f %4f %4f\n", l, t, + width, height, fl, ft, fr, fb); + +#ifdef ACCEL_CP + BEGIN_RING(22); + + /* Note: we can't simply setup 3D surface at the same location as the front buffer, + some apps may draw offscreen pictures out of the limitation of radeon 3D surface. + * Well, not with current XAA, but the screen itself may extend beyond the 2048x2048 limit. + */ + OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset); + + OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, 16)); + /* RADEON_SE_VF_CNTL */ + OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | + RADEON_CP_VC_CNTL_PRIM_WALK_RING | + (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); + + OUT_RING(F_TO_DW(l)); + OUT_RING(F_TO_DW(t)); + OUT_RING(F_TO_DW(fl)); + OUT_RING(F_TO_DW(ft)); + + OUT_RING(F_TO_DW(r)); + OUT_RING(F_TO_DW(t)); + OUT_RING(F_TO_DW(fr)); + OUT_RING(F_TO_DW(ft)); + + OUT_RING(F_TO_DW(r)); + OUT_RING(F_TO_DW(b)); + OUT_RING(F_TO_DW(fr)); + OUT_RING(F_TO_DW(fb)); + + OUT_RING(F_TO_DW(l)); + OUT_RING(F_TO_DW(b)); + OUT_RING(F_TO_DW(fl)); + OUT_RING(F_TO_DW(fb)); + + /*OUT_ACCEL_REG(RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH);*/ + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); + + ADVANCE_RING(); +#else + BEGIN_ACCEL(19); + + /* Note: we can't simply setup 3D surface at the same location as the front buffer, + some apps may draw offscreen pictures out of the limitation of radeon 3D surface. + */ + OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset); + + /* When cp is enabled, the final drawing can be done by sending a type-3 packet. + But it doesn't seem to give much noticeable performance improvement, + may not worth of bloating up the code. + */ + OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST | + RADEON_VF_PRIM_WALK_DATA | + 4 << RADEON_VF_NUM_VERTICES_SHIFT)); + + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(l)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(t)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fl)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(ft)); + + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(r)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(t)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fr)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(ft)); + + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(r)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(b)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fr)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fb)); + + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(l)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(b)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fl)); + OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fb)); + + /*OUT_ACCEL_REG(RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH);*/ + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); + + FINISH_ACCEL(); +#endif +} + +#undef FUNC_NAME +